The present invention relates to a digital frequency divider circuit.
Frequency divider circuits are among the basic circuits of digital technology. Frequency dividers are digital circuits wherein the input frequencies are integer multiples of the output frequencies. Such circuits are used for example in radiofrequency technology, where there exists continual demand for the development of circuits with ever higher clock rates or frequencies. In order to realize frequency divider circuits, usually a plurality of gates are connected in series in a combinatorial part of the circuit, so that, for each state change of the input signal, many gates are switched within one clock period.
Such a frequency divider is described for example in U.S. Pat. No. 5,065,415 and German patent DE 40 08 385 C2. In order to generate an output signal, a plurality of prescalers are cascaded, of which each prescaler can be changed over between the operating modes divide-by-2 and divide-by-3. Each prescaler is connected to a device which enables the state of the respective prescaler to be set in such a way that, within a division cycle of the frequency divider: the individual prescalers divide by 2 or by 3 in a first time period within the division cycle and divide by 2 in the subsequent time period within the same division cycle.
The maximum possible input frequency of a frequency divider is thus limited by the sum of the signal propagation times of the series-connected gates.
In the past, essentially two solution approaches have emerged for combating this problem. Firstly, attempts are made to further develop the semiconductor technology used such that the signal propagation times become ever shorter. Another procedure consists in reducing as far as possible the number of gates to be traversed. This is possible for example by using a PN (pseudo noise) code.
However, even the use of fast semiconductor technology or the use of PN codes often no longer satisfies the requirements for ever higher-frequency circuits. In particular the demands for frequency divider circuits with an arbitrarily adjustable divider ratio and demands for an adjustable duty ratio (duty cycle) of the output signal cause the known methods to encounter frequency limits.
It is accordingly an object of the invention to provide a frequency divider, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for a frequency divider with an adjustable divider ratio that can process higher clock rates.
With the foregoing and other objects in view there is provided, in accordance with the invention, a frequency divider, comprising:
an input terminal for receiving an input signal with a first clock frequency and an output terminal for an output signal;
a state register, encompassing n bits, for storing a register state from a multiplicity of register states;
a decoder connected to the state register, the decoder assigning to the register states in each case an m-bit word, a plurality of second n-bit words, and state-dependent variables;
a loading device connected to the state register and configured to write, depending on an adjustable divider ratio and the state-dependent variables, one of the n-bit words to the state register at a second clock frequency corresponding to the frequency of the input signal divided by m; and
a parallel-serial converter connected to the loading device for reading in the m-bit words in parallel at the second clock frequency and outputting the m-bit words serially as the output signal.
In accordance with a further feature of the invention, there is provided, for the special case divider ratios of TV=2 and TV=3, respective additional circuitry for bypassing the register and the decoder, connected to an internal bus connected between an input and the output of the multiplexer.
In other words, the objects of the invention are achieved with a frequency divider that comprises: a terminal for an input signal with a first clock frequency and a terminal for an output signal, a state register, comprising n bits (n is an integer), for storing a register state from a multiplicity of register states, a decoder, which is connected to the state register, and which assigns to the register states in each case an m-bit word, a plurality of second n-bit words and state-dependent variables, a loading device, which, depending on an adjustable divider ratio and the state-dependent variables, writes one of the n-bit words to the state register with a second clock frequency, which corresponds to that of the input signal divided by m and a parallel-serial converter, which reads in the m-bit words in parallel in the second clock frequency and outputs them serially as output signal.
The invention is based on the principle that the output signal of a frequency divider is not generated and output in a bitwise manner, rather the output signal is decomposed into blocks each of m bits. Consequently, a time which is m times as long as the clock time of the input signal is available for forming each such m-bit word. Consequently, higher clock rates can be processed. The m-bit words are joined together at an output of the circuit and output serially.
The frequency divider according to the invention has a state register having a multiplicity of counter states. In each case an m-bit word is combined with the states of the state register which word is read in in a parallel-serial converter and is output serially. The state register is consequently operated with a clock which is m times as slow as the input clock. Consequently, for the formation of the m-bit words, and for the formation of further variables respectively dependent on the counter state, the m-fold time is available, relative to a conventional frequency divider circuit wherein in each case a multiplicity of gates must be traversed per input clock period in the combinatorial part of the circuit. The assignment of the state-dependent variables and of further n-bit words is effected in a decoder. The n-bit state register is loaded anew with a subsequent state by the loading device in each case after a slow clock period has elapsed. For this, the loading device requires the n-bit words generated in the decoder, the loading of the state register being dependent, of course, on the divider ratio set. This is because the loading of the state register with a new n-bit word can be equated to jumping to a new state, after which in each case new, dependent one- and multi-bit variables are again generated.
The counter states of the n-bit state register can be coded with a selectable code. Of course, the state-dependent further n-bit words which define the respective succeeding state must then likewise be defined in accordance with the code used in the state register.
The present circuit advantageously has an adjustable duty ratio. At the same time, however, the present frequency divider circuit manages with a limited number of register states since, although the order of the register states that are respectively loaded one after the other depends on the divider ratio set, the divider nonetheless has recourse, in principle, independently of the duty ratio set, to the same set of register states, only in a different order.
Since most of the circuit according to the invention is operated with a comparatively slow clock, that is to say a clock with a frequency m times slower than the input frequency, the circuit design is simplified to a significant extent with regard to drivers and line lengths. The present frequency divider continues to operate correctly even when the divider ratio is changed over to a different value at an arbitrary point in time while the frequency divider is operating.
In accordance with an added feature of the invention, the parallel-serial converter is realized as a multiplexer. Multiplexer circuits are known to be extremely reliable.
In accordance with an additional feature of the invention, the bit width of the counter states is equal to the bit width of the m-bit words, and consequently the relationship m=n holds true. By way of example, the use of 4-bit blocks is advantageous for achieving significantly higher clock frequencies, with the result that the decoder circuit can be operated with a quarter of the input clock frequency. Consequently, quadruple the time is available for the formation of the 4-bit blocks. Given the same bit width of the state register, 2n=24=16 follows for the number of register states of the state register.
In accordance with another feature of the invention, the duty ratio (duty cycle) of the output signal of the frequency divider can be set in a simple manner by defining the coding of the m-bit words of the register in accordance with the desired duty ratio.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a frequency divider, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.